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K. Tomasena, J. F. Sevillano, J. Pérez, A. Cortés, and I. Vélez. A Transaction Level Assertion Verification Framework in SystemC: an Application Study. The Second International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS), Sliema, Malta, 11th-16th October 2009

Digital Object Identifier: 10.1109/CENICS.2009.24

Abstract:

This paper presents a new transaction level assertion verification framework built on top of SystemC to support the integration of Assertion Based Verification in a Model Driven Design methodology. A key point of the proposed framework is that it enables decoupling the work of the design and verification teams. This is possible thanks to data introspection capabilities; the fact that the assertions are not embedded in the design model code; and the abstraction in the property specification. Thus, the two teams can work in parallel starting from the natural language specification, reducing the development time.